The performance of a computer system can be enhanced by the use of a memory hierarchy. For example, a three tiered memory can be constructed from low, medium, and high speed memories. A low speed memory may be a magnetic disk for low cost, bulk storage of data. A medium speed memory may be constructed from DRAMs for use as the computer system's main memory. A high speed memory may employ SRAMs for use as a processor cache memory. The theory behind memory hierarchy is to group code (instructions) and other data to be executed by the system processor in the highest speed memory. Since high speed memory is typically the most expensive memory available, economics dictate that it be relatively small. Main memory consisting of DRAMs is denser and less expensive than a cache memory with SRAMs, and can therefore be significantly larger than the cache memory.
During operation, instructions and other data are transferred from system memory to the cache memory in order to have quick access to the variables of the currently executing program. As additional data, not in the cache, is required, such data is transferred from the main memory by replacing selected data in the cache. Various replacement algorithms are utilized to determine which data is replaced.
Irrespective of whether or not a cache memory is employed, increasing the response time of the DRAM memory can further improve system performance. There are several ways to increase the speed of a DRAM memory without changing the basic structure of the DRAM. For example, "interleaving" involves the creation of two banks of memory, with odd addresses in one bank and even addresses in the other. By this technique, one bank may be precharged while the other is being accessed. If a DRAM access normally takes two clock cycles, sequential accesses may be accomplished in one clock cycle each.
Another technique for speeding up DRAM access is referred to as "fast page mode". In a fast page mode, a DRAM controller activates a row line in a memory page and then strobes sequential column lines. Since the row line does not have to be precharged between accesses on the same page, the speed of reads and writes to the DRAM is increased. However, if sequential reads and writes are not to the same page, pages are continually being opened and closed and the fast page mode provides little or no performance advantage.